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-- Company: 
-- Engineer: 
-- 
-- Create Date: 2022/08/03 22:15:49
-- Design Name: 
-- Module Name: MYLATCH - ART1
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY MYLATCH IS
  PORT (
    D : IN STD_LOGIC;
    ENA : IN STD_LOGIC;
    Q : OUT STD_LOGIC);
END MYLATCH;

ARCHITECTURE ART1 OF MYLATCH IS
  SIGNAL S0 : STD_LOGIC;
BEGIN
  PROCESS (D, ENA)IS
  BEGIN
    IF ENA = '1' THEN
      S0 <= D;
    END IF;
    Q <= S0;
  END PROCESS;
END ART1;